1. Field of the Invention
The present invention relates to logic gate structures, and more particularly, to an electrically erasable and programmable read-only memory (EEPROM) and to Flash EEPROMs employing metal-oxide-semiconductor (MOS) floating gate structures.
2. Description of the Related Art
Electrically erasable and programmable non-volatile semiconductor devices, such Flash EEPROMs are well known in the art. One type of Flash EEPROM employs metal-oxide-semiconductor (MOS) floating gate devices. Typically, electrical charge is transferred into an electrically isolated (floating) gate to represent one binary state while an uncharged gate represents the other binary state. The floating gate is generally placed above and between two regions (source and drain) spaced-apart from each other and separated from those regions by a thin insulating layer, such as a thin oxide layer. An overlying gate is disposed above the floating gate provides capacitive coupling to the floating gate, allowing an electric field to be established across the thin insulating layer. “Carriers” from a channel region under the floating gate are tunneled through the thin insulating layer into the floating gate to charge the floating gate. The presence of the charge in the floating gate indicates the logic state of the floating gate, i.e., 0 or 1.
Several methods can be employed to erase the charge in a floating gate. One method applies ground potential to two regions and a high positive voltage to the overlying gate. The high positive voltage induces charge carriers, through the Fowler-Nordheim tunneling mechanism, on the floating gate to tunnel through an insulating layer that separates the overlying gate and the floating gate into the overlying gate. Another method applies a positive high voltage to a source region and grounds the overlying gate. The electric field across the layer that separates the source region and the floating gate is sufficient to cause the tunneling of electrons from the floating gate into the source region.
Typically, one control gate and one floating gate form a memory cell and store only one piece of data. Accordingly, to store a large number of data, a large number of memory cells are needed. Another problem faced with traditional memory cells is miniaturization. Shrinking the scale of transistors has made it more difficult to program the floating gate devices, and reduces the ability of the floating gate devices to hold a charge. When the overlaying gate cannot induce enough voltage onto the floating gate, the floating gate cannot retain enough charge for a meaningful read-out. Therefore, the traditional transistor layout is reaching a limitation in miniaturization.